3d7523 d a ta delay devices, i n c. ? 3 monolithic manchester encoder/decoder (series 3d7523) features packages ? all-silicon, low-power cmos technology ? encoder and decoder function independently ? encoder has buffered clock output ? ttl/cmos compatible inputs and outputs ? vapor phase, ir and wave solderable ? auto-insertable (dip pkg.) ? low ground bounce noise ? maximum dat a rat e : 50 mbaud ? data rate range: 15% ? lock-in time: 1 bit f o r mechanical dimensions, click here . f o r package marking details, click here . 14 13 12 11 10 9 1 2 3 4 5 6 ci cen cout di n r esb vd d cb uf l oop txe n b dout b txb 3 d 752 3-x x x d i p ( . 300 ) 3 d 752 3g -x x x g u ll w i ng (.3 00) 3 d 752 3d -x x x s o ic ( . 150 ) n rx 8 7 gnd tx functional description pin descriptions encoder: cin clock input din data input resb res e t cen clock buffer enable txenb transmit enable cb uf b u f f e red clock tx,txb transmitted signal decoder: rx received signal cout recov e red clock doutb recov e red data common: loop loop enable vdd +5 volts gnd ground the 3d7523 is a monolithic cmos manchester encoder/decoder combo chip. the device uses bi-phase-level encoding to embed a clock signal into a data stream for transmission across a communications link. in this encoding mode, a logic one is represent ed by a high-to-low transition in the center of the bit cell, while a logi c zero is represented by a low-to-high transition. the manchester encoder combines the clock (cin) and data (din) into a single bi-phase-level signal (tx). an inve rted version of this signal (txb) is also available. the data baud rate (i n mbaud) is equal to the input clock frequency (in mhz). a replica of the clo ck input is also available (cbuf). the encoder may be reset by setting the resb input low; otherwise, it should be left high. the tx and txb signals may be disabled (high-z) by setting txenb high. similarly, cbuf may be disabled by setting cen low. under most operating conditions, tx and txb are always enabled, and cbuf is not used. with this in mi nd, the 3d7523 provides internal pull- down resistors on cen and txenb, so that most users can leave these inputs uncommitted. the manchester decoder accepts the embedded-clock signal at the rx input. the recovered clock and data signals are presented on cout and doutb, respec tively, with the data signal inverted. the operating baud rate (in mbaud) is specified by the das h number of the device. the input baud rate may vary by as much as 15% from the nominal device baud rate wit hout compromising the integrity of the information received. because the decoder is not pll-bas ed, it does not require a long preamble in order to lock onto the received signal. rather, the device requires at most one bit cell before the data pr esented at the output is valid. this is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off. normally, the encoder and decoder function independently. ho wever, if the loop input is set high, the encoded tx signal is fed back internally into the decoder and the rx input is ignored. this feature is useful for diagnostics. the loop input has an inte rnal pull-down resistor and may be left uncommitted if this feature is not needed. ? 2006 data delay dev i ces doc #06003 data delay devices, inc. 1 5/8/2006 3 mt. prospect ave. clifton, nj 07013
3d7523 table 1: part number specifications pa rt decoder ba ud ra te (mbaud) n u m b e r n o m i n a l mi n i m u m m a x i m u m 3 d 7 5 2 3 - 0 . 5 0 . 5 0 0 . 4 3 0 . 5 7 3 d 7 5 2 3 - 1 1 . 0 0 0 . 8 5 1 . 1 5 3 d 7 5 2 3 - 5 5 . 0 0 4 . 2 5 5 . 7 5 3 d 7 5 2 3 - 1 0 1 0 . 0 0 8 . 5 0 1 1 . 5 0 3 d 7 5 2 3 - 2 0 2 0 . 0 0 1 7 . 0 0 2 3 . 0 0 3 d 7 5 2 3 - 2 5 2 5 . 0 0 2 1 . 2 5 2 8 . 7 5 3 d 7 5 2 3 - 5 0 5 0 . 0 0 4 2 . 5 0 5 7 . 5 0 note: a n y baud rate betw een 0.5 and 50 mbaud not show n is also av ailable at no extra cost. application notes encoder the encoder presents at its outputs the true and the complimented encoded data. the high-to- low time skew of the selected data output should be budgeted by the user, as it relates to his applic ation, to s a tis f ac torily es timate the distortion of the transmitted data stream. such an estimate is very useful in determining the the manchester encoder subsystem samples the data input at the rising edge of the input clock. the sampled data is used in conjunction with the clock rising and falling edges to generate the by- phase level manchester code. the encoder employs the timing of the clock rising and falling edges (duty cycle) to implement the required coding scheme, as shown in figure 1. to reduce the difference between the output data high time and low time, it is essential that the deviation of the input clock duty cycle from 50/50 be minimized. functionality and margins of the data link, if a manchester decoder is used to decode the received data. r eset (r esb) cl ock (ci n ) da t a (di n ) t r an sm it (t x ) t r an sm it (t x b ) t ds t dh figur e 1 : t i m i ng d i a g r a m ( e nc ode r ) 1/ f c 10110010 10110010 ( l ef t h i g h f o r n o r m al op er at i o n ) t 2h t 2l t 1h t 1l doc #06003 data delay devices, inc. 2 5/8/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7523 application notes (cont?d) decoder to one ov er tw ice the baud rate . otherwis e , the input is presented at the clock output unchanged, shifted in time. therefore, the clock duty cycle is strongly dependent on the baud rate, as this will affect the clock-high duration. the manchester decoder subsystem samples the input at precise pre-selected intervals to retrieve the data and to recover the clock from the received data stream. its architecture comprises finely tuned delay elements and proprietary circuitry which, in conjunc tion with other circuits, implement the data decoding and clock recovery function. the clock output falling edge is not operated on by the c l oc k rec o very c i rc uitry. it, therefore, preserves more accurately the clock frequency information embedded in the transmitted data. it can therefore be used, if desired, to retrieve clock frequency information. typically, the encoded data transmitted from a source arrives at the decoder corrupted. such corruption of the received data manifests itself as jitter and/or pulse width distortion at the decoder input. the instantaneous deviations from nominal baud rate and/or pulse width (high or low) adversely impact the data extraction and clock recovery function if their published limits are exceeded. see table 4, allow e d baud rate/duty cy cle. the decoder, being a self- timed device, is tolerant of frequency modulation (jitter) present in the input data stream, provided that the input data pulse width variations remain within the allowable ranges. input signal characteristics the 3d7523 inputs are ttl compatible. the user should assure him/herself that the 1.5 volt ttl threshold is used when referring to all timing, especially to the input clock duty cycle (encoder) and the received data (decoder). power supply and temperature considerations cmos integrated circuitry is strongly dependent on power supply and temperature. the monolithic 3d7523 manchester encoder/decoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power s upply and/or temperature. nevertheless, optimum performance is achieved by providing a stable power supply and a clean ground plane, and by placing a bypass capacitor (0.1uf typically) as close to the device as possible. the decoder presents at its outputs the decoded data (inverted) and the recovered clock. the decoded data is v a lid at the rising edge of the clock. the clock recovery function operates in two modes dictated by the input data stream bit sequence. when a data bit is succeeded by its inverse, the clock recovery circuit is engaged and forces the clock output low for a time equal cl ock (cl k ) re ce i v e d (rx ) figur e 2 : t i m i ng d i a g r a m ( d e c ode r ) t c de code d 1011001 e ncode d 1011001 0 da t a (d at b) t cl t cw l t cd doc #06003 data delay devices, inc. 3 5/8/2006 3 mt. prospect ave. clifton, nj 07013
3d7523 device specifications table 2: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v dd - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd +0. 3 v input pin current i in - 1 0 1 0 m a 2 5 c storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 3: dc electrical characteristics (-40c to 85c, 4.75v to 5.25v) p a r a m e t e r s y m b o l m i n m a x units n o t e s static supply current* i dd 5 m a high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v high level input current i ih 1 . 0 a v ih = v dd low level input current i il 1 . 0 a v il = 0v high level output current i oh - 4 . 0 m a v dd = 4.75v v oh = 2.4v low level output current i ol 4 . 0 m a v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 n s c ld = 5 pf *i dd (dy namic) = 2 * c ld * v dd * f input capacitance = 10 pf ty pical w here: c ld = average capacitance load/pin (pf) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz) table 4: ac electrical characteristics (-40c to 85c, 4.75v to 5.25v, except as noted) parameter symbol m i n t y p m a x u n i t s n o t e s input baud rate (encoder) f bn 5 0 m b a u d clock f r equency f c 5 0 m h z data set-up to clock rising t ds 3 . 5 n s data hold from clock rising t dh 0 n s t x high-low time skew t 1h - t 1l - 3 . 5 3 . 5 n s 1 t x b high-low time skew t 2h - t 2l - 2 . 0 2 . 0 n s 1 t x - t x b high/low time skew t 1h - t 2l - 3 . 0 3 . 0 n s 1 nominal input baud rate (decoder) f bn 5 5 0 m b a u d allow ed input baud rate deviation f b - 0 . 1 5 f bn 0 . 1 5 f bn mbaud 0c to 70c 25c, 5.00v allow ed input baud rate deviation f b - 0 . 0 5 f bn 0 . 0 5 f bn mbaud 4.75v to 5.25v allow ed input baud rate deviation f b - 0 . 0 3 f bn 0 . 0 3 f bn mbaud -55c to 125c 4.75v to 5.25v allow ed input duty cy cle 4 2 . 5 5 0 . 0 5 7 . 5 % bit cell t i me t c 1000/f b n s input data edge to clock falling edge t cl 0 . 7 5 t c n s clock w i dth low t cw l 500/f bn n s 2ns or 5% clock f a lling edge to data t r ansition t cd 3 . 0 4 . 0 5 . 0 n s notes: 1: assumes a 50% duty cycle clock input doc #06003 data delay devices, inc. 4 5/8/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7523 automated testing - monolithic products test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1/(2*baud) period: per in = 1/baud note: the above conditions are for test only and do not in any way restrict the operation of the device. out tr i g in tr i g f i g u r e 3: t est s e t u p de v i ce unde r t est (d u t ) di gi t a l s c op e w avefo r m ge ne ra t o r out in com p ut e r sy st em pr in t e r figur e 4 : t i m i ng d i a g r a m t pl h t ph l per in pw in t ris e t fa l l 0. 6v 0. 6v 1. 5v 1. 5v 2. 4v 2. 4v 1. 5v 1. 5v v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #06003 data delay devices, inc. 5 5/8/2006 3 mt. prospect ave. clifton, nj 07013
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